sFPDP Gen3 (VITA 17.3) Release 2.8 now available! This release adds support for ASIC devices as well as MicroSemi PolarFire FPGAs. We have partnered with Cadence to prepare the IP for ASIC use, resulting in a more robust Clock and Reset Domain Crossing strategy as well as a unified clocking and reset structure implemented across all device families. The v2.8 release represents a major update and is recommended for all users.
Contact us at firstname.lastname@example.org or visit us at www.streamdsp.com for more information.
If you are a current sFPDP Gen3 (VITA 17.3) customer with an active maintenance agreement and wish to receive this new update, simply respond to this email and let us know. If you are a sFPDP (VITA 17.1) customer and would like to consider sFPDP Gen3 for your next program we would be happy to answer any questions you might have.